The present disclosure relates to a clock transfer circuit configured to perform transfer from a clock with which input data is synchronized to another clock having a different frequency and to output such data.
A clock transfer circuit is configured to perform transfer from a clock with which input data is synchronized to another clock having a different frequency and to output such data. In the clock transfer circuit, e.g., a 2-port RAM is used to control a write address and a read address with a moderate distance therebetween, thereby performing transfer from a clock with which write data is synchronized to another clock having a different frequency and reading and transmitting such data.
If address conflict occurs due to gradual narrowing of the distance between the write address and the read address, so-called “failure in memory address control” occurs. Conventionally, in order to reduce or prevent such address conflict, the write address and the read address are compared with each other, and the addresses are reset when the distance between the addresses is gradually narrowed to cause the address conflict.
According to Japanese Unexamined Patent Publication No. 2009-218885, a write address is converted into a Gray-code format, and retiming is performed using a read clock. In this manner, transfer between clocks is performed.